Daniele Cesarini

Vice-chair for Research

CINECA

He graduated in Computer Engineering from the University of Bologna (Italy) in 2014, where he also earned his Ph.D. in Electronics, Telecommunications, and Information Technologies Engineering in 2019.


He is currently an HPC Specialist at Cineca High Performance Computing department where he works in the area of performance optimization and evaluation of next-generation HPC architectures to improve the roadmap of CINECA’s HPC infrastructures. His range of expertise include parallel programming model, shared and distributed memory systems, high-performance computer architectures and runtime systems. His research interests also concern the development of SW-HW co-design strategies as well as algorithms for parallel programming support for energy efficient HPC systems. He has also an active role in the energy efficient HPC activities of CINECA where his work is focused to improve the power efficiency of the CINECA’s datacenter.

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